In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PPA) metrics. Recently, reinforcement learning (RL) has emerged as a promising technique for improving placement quality, especially macro placement. However, current RL-based placement methods suffer from long training times, low generalization ability, and inability to guarantee PPA results. A key issue lies in the problem formulation, i.e., using RL to place from scratch, which results in limits useful information and inaccurate rewards during the training process. In this work, we propose an approach that utilizes RL for the refinement stage, which allows the RL policy to learn how to adjust existing placement layouts, thereby receiving sufficient information for the policy to act and obtain relatively dense and precise rewards.

Global routing plays a critical role in modern chip design. The routing paths generated by global routers often form a rectilinear Steiner tree (RST). Recent advances from the machine learning community have shown the power of learning-based route generation; however, the yielded routing paths by the existing approaches often suffer from considerable overflow, thus greatly hindering their application in practice.We propose NeuralSteiner, an accurate approach to overflow-avoiding global routing in chip design. The key idea of NeuralSteiner approach is to learn Steiner trees: we first predict the locations of highly likely Steiner points by adopting a neural network considering full-net spatial and overflow information, then select appropriate points by running a graph-based post-processing algorithm, and finally connect these points with the input pins to yield overflow-avoiding RSTs. NeuralSteiner offers two advantages over previous learning-based models. First, by using the learning scheme, NeuralSteiner ensures the connectivity of generated routes while significantly reducing congestion. Second, NeuralSteiner can effectively scale to large nets and transfer to unseen chip designs without any modifications or fine-tuning. Extensive experiments over public large-scale benchmarks reveal that, compared with the state-of-the-art deep generative methods, NeuralSteiner achieves up to a 99.8\% reduction in overflow while speeding up the generation and maintaining a slight wirelength loss within only 1.8\%.

In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PP A) metrics.

By 2033, the global AI chip market is projected to reach $700bn (£620bn) a year, outstripping the whole of today's semiconductor market. By 2033, the global AI chip market is projected to reach $700bn (£620bn) a year, outstripping the whole of today's semiconductor market. Britain's legacy in chip design is world-class, and we could supply up to 5% of global demand if we get our act together Thu 13 Nov 2025 13.26 ESTLast modified on Thu 13 Nov 2025 14.08 EST The UK is in a uniquely promising position, far too little understood, to play a lucrative role in the coming era of artificial intelligence - but only if it also grabs the opportunity to start making millions of computer chips. AI requires vast numbers of chips and we could supply up to 5% of world demand if we get our national act together. Our legacy in chip design is world-class, starting with the first general-purpose electronic computer, the first electronic memory and the first parallel computer.

Welcome to our monthly digest, where you can catch up with any AIhub stories you may have missed, peruse the latest news, recap recent events, and more. This month, we attend AIES and ECAI, learn about policy design for two-sided platforms, discover how to balance speed and physical laws in atomic-scale simulations, and find out more about machine learning for chip design. October has been a busy month on the conference front. Over in Madrid, researchers gathered for the conference on Artificial Intelligence, Ethics, and Society (AIES) . The event featured two keynote talks, panel discussions and poster sessions.

Lorenzo Servadei and his team at Sony AI are focused on researching and developing machine learning models to aid chip design and manufacturing. In this interview, Lorenzo tells us more about Electronic Design Automation, and how machine learning has been added into the mix to further advance the field of semiconductor chip design. What was your inspiration for pursuing a career in AI and semiconductors? When I was pursuing my Master's degree, I studied subjects related to traditional computer science and algorithmics - before AI was seen as a specific area of study - which led me into the field of software development. While working in software development, I had the opportunity to join a semiconductor company that was seeking AI experts, which allowed me to explore the algorithmic aspects of AI.

In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PP A) metrics.

Global routing plays a critical role in modern chip design. The routing paths generated by global routers often form a rectilinear Steiner tree (RST).

In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PPA) metrics. Recently, reinforcement learning (RL) has emerged as a promising technique for improving placement quality, especially macro placement. However, current RL-based placement methods suffer from long training times, low generalization ability, and inability to guarantee PPA results. A key issue lies in the problem formulation, i.e., using RL to place from scratch, which results in limits useful information and inaccurate rewards during the training process. In this work, we propose an approach that utilizes RL for the refinement stage, which allows the RL policy to learn how to adjust existing placement layouts, thereby receiving sufficient information for the policy to act and obtain relatively dense and precise rewards.